For example, the SH-5 CPU can be suspended ... In this case, the parameters of the matching operation are stored in memory-mapped registers and can be read for processing by the interrupt handler.

These latencies and computational delays depend on the processor architecture as well as the complexity of the control algorithms. For example, a 32 bit Arm Cortex M3 will have a much better real-time ...

A C.I.P. Catalogue record for this book is available from the Library of Congress. ISBN 0-387-25280-0 e-ISBN 0-387-25281-9 Printed on acid-free paper. ISBN 978-0387 ...