Design-Reuse6y
RISC-V processor - 32 bit, 5-stage pipeline
The L50(F) is a medium-sized, efficient 32-bit embedded RISC-V processor aimed at embedded systems with mid-range processing requirements. The core has a 5-stage pipeline. The L50F has a floating ...
Design-Reuse1y
Maven Silicon's RISC-V Processor IP Verification Flow
The approach is to build a pre-verified synthesizable RISC-V IP fundamental IP building blocks library and create any kind of multi-stage pipeline RISC-V processor using this library. Finally, the ...
Hackaday6y
A RISC-V That The Rest Of Us Can Understand
There is great excitement in the world of microprocessors, surrounding the RISC-V architecture. This is an open source modular instruction set specification that has seen implementations on FPGAs ...